Dc amplifier and semiconductor integrated circuit therefor

ABSTRACT

A rectangular parallelepiped projecting portion  21  having a height of H B  and a width of W B  is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion  21 . A source and a drain are formed on both sides of the gate electrode  26  to form a MOS transistor. The MOS transistor configures a DC amplifier. The DC amplifier includes a differential amplification circuit having MOS transistors  61  and  62 , thereby realizing a high-gain DC amplifier.

TECHNICAL FIELD

The present invention relates to a DC amplifier formed on the substrateof a semiconductor integrated circuit, and the semiconductor integratedcircuit for the DC amplifier.

BACKGROUND ART

In the conventional production process of a MOS transistor, a thermaloxide film is formed on the silicon surface in a high temperatureenvironment of 800° C., and a MOS transistor is produced using a thermaloxide film as a gate insulating film.

It is requested to form an oxide film in a lower temperature environmentto enhance the production efficiency of a semiconductor. To realize thisrequest, for example, the patent document 1 discloses the technology offorming an insulating film in a low temperature plasma atmosphere.

In the wireless communication field of mobile telephones, etc., acircuit is integrated to achieve smaller and lower cost equipment.

To demodulate a radio signal, there is a super heterodyne system ofconverting a received signal to an intermediate frequency, amplifyingthe frequency, and converting the result to a baseband signal, and adirect conversion system of converting a received signal directly to abaseband signal.

The direct conversion system requires no filter, etc. for removing animage generated when conversion to an intermediate frequency signal isperformed. Therefore, a receiver can be configured with a simplercircuit.

In a direct conversion receiver, it is necessary for a mixer to mixlocal oscillation signals having 90° phase difference from a receivedsignal, convert the obtained signals to two baseband signals havingphases orthogonal to each other, and then amplify the baseband signalswith a DC amplifier.

However, since the output signal of the mixer contains a DC offset, theDC offset is also amplified by the DC amplifier, thereby causing aproblem that amplitude gain of a baseband signal cannot be sufficientlyobtained.

To solve the problem, an example is shown in FIG. 7. A circuit forconnecting a capacitor 72 of a relatively large capacity to absorb theDC offset to the input side of an operational amplifier 71 isdemonstrated.

Patent Document 1: Japanese Published Patent Application No. 2002-261091(FIG. 1, paragraph 0022, etc.)

Patent Document 2: Japanese Published Patent Application No. 2002-217769

Since it is hard to form the capacitor 72 with a capacity large enoughto remove the DC offset shown in FIG. 7 on the substrate of anintegrated circuit, an external capacitor is used. By using an externalcapacitor, it is necessary to provide a terminal 73 for connecting thecapacitor to the semiconductor integrated circuit, and the number ofexternal terminals available as input/output terminals of a signaldecreases. Therefore, as the number of necessary terminals is increased,the size of the entire system with the external capacitor becomesproblematic. By using the external capacitor components cost isincreased.

When a MOS transistor in a direct conversion receiver configures a DCamplifier, the MOS transistor has higher 1/f noise than a bipolartransistor. Accordingly, it is necessary to take measures to reduce the1/f noise.

DISCLOSURE OF THE INVENTION

The present invention aims at realizing a high-gain DC amplifier, andalso aims at reducing the distortion of the signal in the DC amplifier.

The DC amplifier according to the present invention is formed on thesubstrate of a semiconductor integrated circuit, and includes adifferential amplification circuit. This includes an MIS field-effecttransistor in which a projecting portion is formed by a siliconsubstrate having a first crystal surface as a primary surface and asecond crystal surface as a side surface. Terminated hydrogen on thesilicon surface is removed in a plasma atmosphere of an inert gas, and agate insulating film is formed on at least a part of the top surface andthe side surface of the projecting portion at a temperature at or lowerthan approximately 550° C. in the plasma atmosphere. A gate is formed onthe gate insulating film, and a drain and a source are formed on bothsides enclosing the gate insulating film of the projecting portion.

According to the invention, by decreasing the damage of the siliconsubstrate and enhancing the evenness, the variance of the features (forexample, a threshold voltage, etc.) of the MIS field-effect transistorcan be reduced. Thus, the DC offset and 1/f noise generated in the DCamplifier can be decreased. Therefore, the gain of the DC amplifier canbe increased, and the frequency characteristic of the DC amplifier canbe improved. As a result, a circuit to compensating for the DC offset isnot required.

Additionally, by generating a three-dimensional gate, and forming a gateinsulating film in a low plasma atmosphere, the effect of channel lengthmodulation can be reduced, and the distortion of a signal in the DCamplifier can be decreased.

Furthermore, by forming a gate insulating film on a different crystalsurface, the current drive capability of a MIS field-effect transistorcan be improved and the device area of the MIS field-effect transistoron the primary surface of a silicon substrate can be made smaller.

In the above-mentioned invention, a channel is formed on the firstcrystal surface of the top surface and the second crystal surface of theside surface of the projecting portion, and the channel width of the MISfield-effect transistor is at least a total of the channel width of thetop surface and the channel width of the side surface.

With the above-mentioned configuration, since a channel is formed on twocrystal surfaces, the characteristic of the MIS field-effect transistorand the current drive capability can be improved.

In the above-mentioned invention, the projecting portion has a topsilicon surface (100) and the side silicon surface (110), with thesource and the drain formed in the left and right areas of theprojecting portion and the projecting portion of the silicon substrateenclosing the gate.

With the above-mentioned configuration, a channel can be formed on thesurfaces (100) and (110) of the silicon substrate. Therefore, thecurrent drive capability of the field-effect transistor can be improved.

In the above-mentioned invention, the DC amplifier includes a p-channelMIS field-effect transistor and a n-channel MIS field-effect transistor,and the gate width of the top surface and the side surface of theprojecting portion of the p-channel MIS field-effect transistor is setsuch that the current drive capability of the p-channel MIS field-effecttransistor can be substantially equal to the current drive capability ofthe n-channel MIS field-effect transistor.

With that configuration, the parasitic capacity of the p-channel MISfield-effect transistor can be substantially equal to the parasiticcapacity of the n-channel MIS field-effect transistor. Consequently, thefeatures of the DC amplifier can be improved, and the noise can bereduced during switching.

In the present invention, the DC amplifier includes first and second MISfield-effect transistors for differential amplification of an inputsignal, and a third MIS field-effect transistor commonly connected tothe source or drain of the first and second MIS field-effect transistorsand configuring a constant current circuit.

The above-mentioned invention also includes a fourth and fifth MISfield-effect transistors connected between the source or the drain ofthe first and second MIS field-effect transistors and the power source,and configures a constant current circuit as a load of the first andsecond MIS field-effect transistors.

With the above-mentioned configuration, the DC offset of thedifferential amplification circuit including the first and second MISfield-effect transistors, the constant current circuit including thethird MIS field-effect transistor, or the constant current circuitincluding the fourth and fifth MIS field-effect transistors can bereduced. Furthermore, the influence of the channel length modulationeffect in the circuits can also be reduced.

The semiconductor integrated circuit according to the present inventionincludes on the same circuit substrate: a circuit including a p-channelMIS field-effect transistor and a n-channel MIS field-effect transistorin which a projecting portion is formed by a silicon substrate having afirst crystal surface as a primary surface and a second crystal surfaceas a side surface, terminal hydrogen on the silicon surface is removedin plasma atmosphere of an inert gas, then a gate insulating film isformed on at least a part of the top surface and the side surface of theprojecting portion at a temperature equal to or lower than about 550° C.in the plasma atmosphere, a gate is formed on the gate insulating film,and a drain and a source are formed on both sides enclosing the gateinsulating film of the projecting portion; and a DC amplifier having adifferential amplification circuit including the p-channel MISfield-effect transistor or the n-channel MIS field-effect transistor.

According to the invention, by reducing the variance of thecharacteristic of the MIS field-effect transistor (for example, athreshold voltage, etc.), the DC offset and the 1/f noise can bereduced. Thus, the gain of the DC amplifier can be enhanced, and thefrequency characteristic of the DC amplifier can be improved, therebyrequiring no additional circuit for compensating for the DC offset.

Furthermore, forming the gate in a three-dimensional structure andcreating the gate insulating film in the low temperature plasmaatmosphere causes the influence of the channel length modulation effectcan be suppressed and the signal distortion in the DC amplifier to bedecreased.

Also, using the above-mentioned p-channel MIS field-effect transistorand the n-channel MIS field-effect transistor for the circuit other thanthe DC amplifier, the distortion of the signal in the circuit can bereduced. Furthermore, the 1/f noise and the DC offset can also bereduced.

In the above-mentioned invention, the DC amplifier is configured by aCMOS circuit including the p-channel MIS field-effect transistor and then-channel MIS field-effect transistor.

With the above-mentioned configuration, the current drive capability ofthe p-channel MIS field-effect transistor can be substantially equal tothe current drive capability of the n-channel MIS field-effecttransistor. Thus, the noise during switching can be symmetric betweenthe positive and negative fields.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of the plasma device using a radial line slotantenna;

FIG. 2 shows the comparison of the interface level density;

FIG. 3 shows the structure of a silicon substrate produced in thesemiconductor producing process according to an embodiment of thepresent invention;

FIG. 4 shows the structure of the MOS transistor produced in thesemiconductor production process according to an embodiment of thepresent invention;

FIG. 5 shows the receiving circuit in the direct conversion system;

FIG. 6 shows the circuit of a DC amplifier; and

FIG. 7 shows the conventional DC amplifier.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention is explained below with referenceto the attached drawings. First, there is a semiconductor productionprocess of forming a gate insulating film (for example, an oxide film)on the silicon substrate at a low temperature using an inert gas in aplasma state, and then the production of a MIS (metal insulatorsemiconductor) field-effect transistor. The method for forming a gateinsulating film is disclosed in Japanese Published Patent ApplicationNo. 2002-261091.

FIG. 1 is a sectional view of the plasma device with a radial line slotantenna to be used in the semiconductor production process.

A vacuum is created in a vacuum container (processing chamber) 11 andargon gas (Ar) is introduced from a shower plate 12. The Ar gas isexhausted from an outlet 11A, and then the gas is switched to a kryptongas (Kr). The pressure in the processing chamber 11 is set at 133 Pa (1Torr).

Then, a silicon substrate 14 is placed on a sample table 13, which has aheating mechanism, and the temperature of a sample is set toapproximately 400° C. If the temperature of the silicon substrate 14 isbetween 200° C. and 550° C., following result is almost the same.

The silicon substrate 14 is cleansed with noble fluoride acid in thepretreatment process performed immediately before, and the unusedcoupling of silicon on the surface is terminated with hydrogen as aresult.

Next, a frequency of 2.45 GHz microwave is supplied from a coaxialwaveguide 15 to a radial line slot antenna 16, and then microwave isintroduced from the radial line slot antenna 16 to the processingchamber 11 through a dielectric plate 17 provided in a portion of thewall. The introduced microwave pumps the Kr gas from the shower plate 12to the processing chamber 11. As a result, a high density Kr plasma isformed immediately below the shower plate 12. If the frequency of theprovided microwave is approximately between 900 MHz and 10 GHz, thefollowing results are almost the same.

With the configuration shown in FIG. 1, the interval between the showerplate 12 and the silicon substrate 14 is approximately 6 cm. The filmcan be formed at a higher speed with the smaller interval.

The plasma can be pumped by introducing the microwave to the processingchamber using another method as described below, without limiting theplasma device to a device using a radial line slot antenna.

By exposing the silicon substrate 14 to the plasma pumped by the Kr gas,the surface of the silicon substrate 14 receives an irradiation of Krions of low energy, and the surface terminated hydrogen is removed.

Then, Kr/O₂ mixed gas having a partial pressure ratio of 97/3 isintroduced from the shower plate 12. At this time, the pressure in theprocessing chamber is to be kept at approximately 133 Pa (1 Torr). Inthe high density pumped plasma, which is a mixture of a Kr gas and an O₂gas, the Kr* and the O₂ molecules in the intermediate pumped stateconflict with each other, and a large amount of atomic oxygen O* isefficiently generated.

In the present embodiment, the atomic oxygen O* oxidizes the surface ofthe silicon substrate 14. However, in the conventional thermal oxidationmethod, oxidation is performed by an O₂ molecule and an H₂O molecule,and a very high process temperature of over 800° C. is required. In theoxidization process using the atomic oxygen performed in the presentembodiment, the oxidization process can be performed at a very lowtemperature of approximately 400° C. To extend the conflict opportunitybetween Kr* and O₂, it is desired that a higher pressure is kept in theprocessing chamber. However, if the pressure is too high, the generatedO* conflicts with each other and is returned to an O₂ molecule state.Therefore, the optimum gas pressure must be maintained.

When the desired silicon oxide film (silicon compound layer) thicknessis formed, the introduction of microwave power is stopped in order toterminate the plasma pumping. Then the Kr/O₂ gas mixture is replacedwith Ar gas, thereby terminating the oxidization process. The Ar gasused before and after the present process, is a less expensivealternative to using Kr as a purge gas. The Kr gas used in this processcan be collected for recycling.

After forming the above-mentioned oxide film, an electrode formingprocess a protective film forming process, hydrogen sintering process,etc. are performed to generate a semiconductor integrated circuitincluding a transistor and a capacitor.

A result of the above-mentioned procedure, the hydrogen content in thesilicon oxide film is lower than 10¹²/cm² in the surface densityconversion on the silicon oxide film of the film thickness of 3 nm.Especially on the oxide film having a small leak current, the hydrogencontent in the silicon oxide film is 10¹¹/cm² or less in the surfacedensity conversion. On the other hand, the oxide film not exposed to theKr plasma before forming the oxide film contains hydrogen of 10¹²/cm² ormore in the surface density conversion.

When the oxidization process is performed with the Kr/O₂ gas introducedafter removing the terminated hydrogen by irradiation with Kr plasma asdescribed above, a very excellent low leak feature is obtained. The leakcurrent at the same voltage as the silicon oxide film formed by theconventional microwave plasma oxidization is reduced by two or threedigits of the leak current. The improvement of the leak current featurehas been confirmed in the production of an integrated circuit using thesilicon oxide film having the film thickness up to about 1.7 nm.

When the surface direction dependency of the silicon/silicon oxide filminterface level density is measured relating to the silicon oxide filmobtained in the above-mentioned semiconductor producing process, a verylow interface level density of about 1×10¹⁰ eV⁻¹ cm⁻² is obtained any ofthe surface direction of the silicon surface.

FIG. 2 shows the Kr/O₂ film formed by the above-mentioned semiconductorproduction process on each of the surfaces (100), (110), and (111) of asilicon substrate, and the results of measuring the interface leveldensity of the conventional thermal oxide film.

As shown in FIG. 2, when the Kr/O₂ film is generated, the interfacelevel density of the semiconductor on any of the surfaces (100), (110),and (111) is 10¹⁰ eV⁻¹ cm⁻² or lower. On the other hand, the interfacelevel density of the conventional thermal oxide film formed in anatmosphere higher than 800° C. is 1.1 times or more on surface (100),and in the above-mentioned semiconductor production process, a highquality insulating film of a low interface level density can be formed.

By lowering the interface level density, the probability of recombininga carrier can be reduced, thereby lowering the 1/f noise.

As to the electric features such as the pressure-resistant feature, thehot carrier resistance, the electric charge QBD (charge-to-breakdown) upto the destruction of the silicon oxide film when a stress currentflows, etc. and the reliability feature, the oxide film formed in thesemiconductor production process possesses qualities equivalent to orhigher than the conventional thermal oxide film.

As described above, by performing the high grade silicon oxidizationprocess in all surface directions at a low temperature (400° C.) usingthe silicon oxidization process with Kr/O₂ high density plasma afterremoving the surface terminated hydrogen, it is considered that theabove-mentioned effect can be obtained by a decreasing hydrogen contentin the oxide film by removing the terminated hydrogen, and by containingan inert gas (Kr for example) in the oxide film. By having a smallamount of hydrogen in the oxide film, there is no weak coupling ofelements in the silicon oxide film, and by containing Kr, the stress inthe film or on the Si/SiO₂ interface is moderated and charge in the filmand the interface level density is reduced. As a result, the electriccharacteristic of the silicon oxide film can be largely improved.

In the above-mentioned semiconductor production process, it isconsidered that the hydrogen density of 10¹²/cm² or less in the surfacedensity conversion, or 10¹¹/cm² or less as a preferred condition, andcontaining Kr 5×10¹¹/cm² or less contributes to the improvement of theelectric characteristics and reliability characteristics of the siliconoxide film.

In the above-mentioned semiconductor process, a silicon nitride film anda silicon oxide and nitride film can be formed using a mixture of aninert gas and a NH₃ gas and a mixture of an inert gas, O₂, and NH₃.

The effect obtained by forming a nitride film is mainly based on thepresence of hydrogen in plasma even after removing the surfaceterminated hydrogen. By containing hydrogen in the plasma, the danglingbond in the silicon nitride film and on the interface forms a couplingof Si—H and N—H and is terminated, and as a result, the electronic trapin the silicon nitride film and on the interface disappear.

It is considered that the effect obtained by forming an oxide andnitride film is caused not only by the decrease in the hydrogen contentin the oxide and nitride film by removing the terminated hydrogen, butalso by some percentage of nitrogen contained in the oxide and nitridefilm. The Kr content in the oxide and nitride film is 1/10th or less ofthe content in the oxide film, and the content of nitrogen is largerthan that of Kr. Since the hydrogen content is small in the oxide andnitride film, the rate of weak couplings in the silicon nitride filmdecreases, and the contained nitrogen moderates the stress in the film,Si/SiO₂, or on the interface. As a result, it is considered that thecharge in the film and the interface level density decreases, and theelectric characteristic of the oxide and nitride film is largelyimproved.

The desired result obtained by forming an oxide film or an oxide andnitride film is not only caused by removing the terminated hydrogen, butis also caused by containing Ar or Kr in the nitride film or the oxideand nitride film. That is, as a result of the above-mentionedsemiconductor production process, the Ar or Kr contained in the nitridefilm moderates the stress on the silicon/nitride film interface.Consequently, the fixed charge in the silicon nitride film and theinterface level density are reduced, and the electric characteristic,especially the 1/f noise, is reduced, thereby largely improving thereliability.

The inert gas used in the above-mentioned semiconductor productionprocess is not limited to Ar gas, and Kr gas, but xenon gas Xe can alsobe used.

Furthermore, after forming a silicon oxide film and a silicon nitridefilm, the pressure in a vacuum container 1 is maintained at 133 Pa (1Torr), a gas of a mixture of Kr/NH₃ at a partial pressure ratio of 98/2is introduced, and a silicon nitride film of about 0.7 nm can be formedon the surfaces of a silicon oxide film and a silicon oxide and nitridefilm.

Thus, a silicon oxide film having a silicon nitride film formed on thesurface, or a silicon oxide and nitride film can be obtained. Therefore,an insulating film having a high dielectric constant can be formed.

To realize the above-mentioned semiconductor production process, inaddition to the device shown in FIG. 1, another plasma process devicecapable of forming a low temperature oxide film can be used. Forexample, it is possible to use a 2-stage shower plate type plasmaprocess device having the first gas emission structure emitting an Ar orKr gas for pumping plasma, and a second gas emission structure, which isdifferent from the first gas emission structure and emits an O₂, NH₃, orN₂/H₂ gas.

Described below is the semiconductor production process according to anembodiment of the present invention. The semiconductor process forms agate insulating film of a MIS field-effect transistor on the surface(100) and the surface (110).

When a p-channel transistor is formed on the surface (111), 1.3 timesthe current drive capability of the surface (100) is obtained. If it isformed on the surface (110), 1.8 times the current drive capability ofthe surface (100) is obtained.

FIG. 3 shows the state of forming projecting portions 23 and 24 havingsurfaces (100) and (110) on a silicon substrate 22 in the semiconductorproduction process according to an embodiment of the present invention.FIG. 4 shows the structures of an n-channel MOS transistor 20 and ap-channel MOS transistor 21 produced in the semiconductor productionprocess according to an embodiment of the present invention. FIG. 4shows a channel formed at the lower portion of the gate oxide film andis indicated by diagonal lines.

As shown in FIG. 3, the silicon substrate 22 having the surface (100) asa primary surface is separated by a device separation area 22 c into twoareas: p-type area A and n-type area B. In area A, the rectangularparallelepiped projecting portion 23 having a height of H_(A) and awidth of W_(1A) is formed on the reference of the surface (100).Similarly, in area B, the projecting portion 24 having a height of H_(B)and a width of W_(1B) is formed.

As shown in FIG. 4, a silicon oxide film is formed by the semiconductorproduction process on the surface of the silicon substrate 22 and thetop surfaces and the side surfaces of the projecting portions 23 and 24.

On the silicon oxide film, polysilicon gate electrodes 25 and 26 areformed, the silicon oxide film is patterned when the polysilicon gateelectrodes 25 and 26 are formed, and gate insulating films 27 and 28 areformed below the polysilicon gate electrodes 25 and 26.

In addition, an n-type impure ion is injected into the areas on bothsides of the gate electrode 25 of the p-type area A, thereby formingn-type diffusion areas 29 and 30 including the projecting portion 23.The n-type diffusion areas 29 and 30 configure the source and the drainof the n-channel MOS transistor 20. Also, in the n-type area B, a p-typeimpure ion is injected into the areas on both sides of the gateelectrode 26, thereby forming p-type diffusion areas 31 and 32 includingthe projecting portion 24. The p-type diffusion areas 31 and 32configure the source and drain of the p-channel MOS transistor 21.

When a predetermined voltage is applied to the gate electrodes 25 and 26of the p-channel MOS transistor 21 and the n-channel MOS transistor 20,a channel indicated by the diagonal lines shown in FIG. 4 is formedbelow the gate oxide films 27 and 28.

The gate width of the surface (100) of the n-channel MOS transistor 20is the sum of W_(1A) on the top surface (top surface of the projectingportion 23) of the projecting portion 23, and W_(2A)/2 on the flatportions of the silicon substrate 22 on the right and left below theprojecting portion 23. Therefore, it is a total of W_(1A)+W_(2A).Similarly, the gate width of the surface (110) of the n-channel MOStransistor 20, that is, the gate widths of the left and right sidesurfaces of the projecting portion 23 are H_(A). Therefore, it is a sumtotal of 2H_(A). The gate width corresponds to the channel width. Thegate length of the n-channel MOS transistor 20 is LgA.

Accordingly, the current drive capability of the n-channel MOStransistor 20 is expressed by μ_(n1)(W_(1A)+W_(2A))+μ_(n2)·2H_(A)·μ_(n1) indicates the electron mobility onthe surface (100) and μ_(n2) indicates electron mobility on the surface(110).

Similarly, the gate width of the surface (100) of the p-channel MOStransistor 21 is the sum of W_(1B) on the top surface of the projectingportion 24, and W_(2B)/2 at the flat portions of the silicon substrate22 on the left and right below the projecting portion 24 respectively.Therefore, it is a total of W_(1B)+W_(2B). The gate width of the surface(110) of the p-channel MOS transistor 21, that is, the gate widths onthe left and right side surfaces of the projecting portion 24 are H_(B).As a result, the gate width is a sum total of 2H_(B). The gate widthcorresponds to the channel width. The gate length of the p-channel MOStransistor 21 is LgB.

Therefore, the current drive capability of the p-channel MOS transistor21 can be expressed by μ_(p1) (W_(1B)+W_(2B))+μ_(p2)·2H_(B). μ_(p1)indicates the Hall mobility on the surface (100), and μ_(p2) indicatesthe Hall mobility on the surface (110).

Thus, by setting the respective heights H_(A) and H_(B) of theprojecting portions 23 and 24, the current drive capability of thep-channel MOS transistor 21 and the current drive capability of then-channel MOS transistor 20 can be balanced. This condition can beexpressed by the following equation.μ_(n1)(W _(1A) +W _(2A))+μ_(n2)·2H _(A)=μ_(p1)(W _(1B) +W_(2B))+μ_(p2)·2 H _(B)

By setting the H_(A) and H_(B) to the values satisfying the equationabove, the current drive capability of the p-channel MOS transistor 21and the current drive capability of the n-channel MOS transistor 20 canbe balanced. In this case, it is not necessary that the channel width ofthe primary surface (for example, the surface (100)) of the p-channelMOS transistor 21 is to be exceedingly larger than the channel width onthe surface (100) of the n-channel MOS transistor 20. Therefore, thedifference between them in parasitic capacity by a gate insulating filmcan be smaller. Thus, when a circuit of a CMOS structure is configuredusing p-channel MOS transistor 21 and n-channel MOS transistor 20,making their parasitic capacity nearly equal, the current valueimbalance caused when the parasitic capacity by the gate oxide film ofthem is charged or discharged can be reduced, and the noise level causedwhen the transistor of the CMOS structure is switched can be lowered.

The height H_(B) of the p-channel MOS transistor 21 can be set suchthat, after setting the height H_(A) of the gate of the n-channel MOStransistor 20 to “0”, the current drive capability of the p-channel MOStransistor 21 can be substantially equal to the current drive capabilityof the n-channel MOS transistor 20.

Since the area of the gate on the primary surface (for example, thesurface (100)) of the silicon substrate of the p-channel or then-channel MOS transistor can be smaller than in the conventionalsemiconductor producing process when the p-channel MOS transistor 21 orthe n-channel MOS transistor 20 is individually formed, the area on theprimary surface on the silicon substrate of the p-channel MOS transistorand the n-channel MOS transistor can be smaller, thereby enhancing theintegration of a semiconductor circuit. Furthermore, since the parasiticcapacities of the p-channel and N-channel MOS transistors can be madesmaller, the switching speed of the MOS transistors can be increased,and the power consumption at the switch can be reduced.

The insulating film formed on the silicon surface is not solely limitedto an oxide film, but a silicon nitride film, a silicon oxide andnitride film, etc. can also be formed.

Described below is the case where a semiconductor integrated circuit fora direct conversion receiver is produced in the semiconductor processaccording to the above-mentioned embodiment.

FIG. 5 shows the important portion of the circuit of the directconversion receiver.

A radio signal received by the antenna 41 is amplified by the low noiseamplifier 42, and inputted to the mixer circuits 43 and 44.

A local signal generated by the local oscillation circuit 45 is inputtedto the other input terminal of the mixer circuit 43, and the localsignal is 90 degrees phase-shifted by the phase shifter 46 and theobtained local signal is inputted to the other input terminal of themixer circuit 44.

In the mixer circuits 43 and 44, the received signals and their localsignals are mixed, and are converted to baseband signals having a 90degree phase shift. Then, the low pass filters 47 and 48 formed by aswitched capacitor filter, etc. attenuate a signal over a predeterminedfrequency, and output a resultant signal to the DC amplifiers 49 and 50.

The DC amplifiers 49 and 50 can perform amplification from a directcomponent, and amplify an input signal to the signal level depending onthe resolution of the A/D converters 51 and 52.

The A/D converters 51 and 52 convert an analog baseband signal to adigital signal, and output the signal to the digital signal processor(DSP) 53.

The DSP 53 performs digital signal processing and demodulates thesignal.

An example of DC amplifiers 49 and 50 is explained below and refers toFIG. 6.

The n-channel MOS transistors 61 and 62 configure a differentialamplification circuit, a signal Vin output from the low pass filter 47or 48 is inputted to the gate of the n-channel MOS transistors 61, and asignal −Vin is inputted to the gate of MOS transistor 62.

The n-channel MOS transistor 63 and the n-channel MOS transistor 64configure a current mirror circuit, and the drain of the MOS transistor63 is commonly connected to the source of the MOS transistors 61 and 62.The drain of the MOS transistor 64 is connected to the power sourcevoltage VDD through the constant current source 65, and the gate of theMOS transistors 63 and 64 is connected to the drain of the MOStransistor 64.

Since the MOS transistors 63 and 64 configure a constant currentcircuit, and the constant current source 65 is connected to the drain ofthe MOS transistor 64, a constant current proportional to the currentsupplied from the constant current source 65 flows through the MOStransistor 63.

The MOS transistors 66 and 67 configure a current mirror circuit, wherethe source is connected to the power source voltage VDD, and the drainis connected to the drain of each of the MOS transistors 61 and 62. Thegates of the MOS transistors 66 and 67 are connected to the drain of theMOS transistor 66. The MOS transistors 66 and 67 function as a load ofthe MOS transistors 61 and 62.

A DC amplifier comprised of the above-mentioned differentialamplification circuit performs differential amplification on the inputsignals Vin and −Vin using the MOS transistors 61 and 62, and theamplified signal, Vo, is output.

By structuring the gate of the MOS transistor of the DC amplifier in athree-dimensional array and forming a gate oxide film in a lowtemperature plasma atmosphere, the influence of the channel lengthmodulation effect of the differential amplification circuit comprised ofthe MOS transistors 61 and 62 can be reduced, and the distortion of asignal in the differential amplification circuit is decreased.Furthermore, since the influence of the constant current (comprised ofthe MOS transistors 66 and 67) at the drain functioning as a load of thedifferential amplification circuit and the channel length modulationeffect of the constant current circuit (comprised of the MOS transistors63 and 64) at the source, the fluctuation of the drain current in thesecircuits can be reduced.

As described above, eliminating the damage of the silicon surface andleveling the surface can reduce the variance of the characteristics (forexample, in threshold voltage, etc.) of the MOS transistors. Therefore,the DC offset of the entire circuit can be reduced. Thus, devices (acircuit, a capacitor, etc.) for removing the DC offset are not required,and the signal gain of the DC amplifier can be enhanced. By enhancingthe signal gain of the DC amplifier, for example, a low resolution D/Aconverter can be used for the A/D converter at the subsequent stage ofthe DC amplifier of the receiving circuit in the direct conversionsystem.

Furthermore, by removing the terminated hydrogen on the silicon surfacein a plasma atmosphere such as argon, etc. and then forming a thin andflat silicon insulating film in a plasma atmosphere including argon,krypton, or xenon including oxygen and a gaseous molecule such asoxygen, nitrogen, etc. and at a lower temperature of 550° C. or less,the interface level density of the silicon surface can be lowered. Thus,the probability of recombination of a carrier can be reduced and the 1/fnoise is decreased. By decreasing the 1/f noise, the S/N ratio of thesignal downconverted by the mixer circuits 43 and 44 can be improved. Asa result, the gain of the DC amplifier can be increased.

Additionally, since the current drive capability of the MOS transistorcan be improved and the device area can be made smaller, the integrationcan be enhanced, and the operation speed can be increased. Furthermore,a large signal gain can be obtained since the operation characteristicof the field-effect transistor of a DC amplifier is prepared, theparasitic capacity can be reduced, the frequency characteristic of thedifferential amplification circuit can be improved, and a DC offset canbe reduced. Thus, since the DC offset and the 1/f noise can be reduced,it is particularly effective for a DC amplifier in the direct conversionsystem where a received signal is directly converted to an audio signal.

A CMOS circuit comprised of an n-channel MOS transistor and a p-channelMOS transistor can also configure a DC amplifier. In this case, theparasitic capacity of the p-channel MOS transistor can be substantiallyequal to the parasitic capacity of the n-channel MOS transistor, and theparasitic capacity can be smaller, thereby increasing the operationspeed, etc. of a circuit. Additionally, the noise caused by theimbalance of a current when a p-channel MOS transistor and an n-channelMOS transistor are turned ON or OFF can be decreased.

The p-channel MOS transistor and the n-channel MOS transistor used inthe frequency conversion circuit, the A/D conversion circuit, thedigital circuit, etc. other than the DC amplifier can be produced in theabove-mentioned semiconductor process.

With the above-mentioned configuration, since the characteristics of thep-channel MOS transistor and the n-channel MOS transistor of othercircuits can be prepared, a DC offset and 1/f noise can be reduced.Additionally, since the current drive capability of the MOS transistorcan be improved, the operation characteristics of a circuit can beimproved.

Furthermore, the channels of the p-channel MOS transistors and then-channel MOS transistors of the DC amplifier or other circuits areformed on different crystal surfaces (for example, the surfaces (100)and (110)) of silicon, and the channel width can be designed such thatthe current drive capability of a p-channel MOS transistor can besubstantially equal to the current drive capability of a n-channel MOStransistor.

With the configuration, the parasitic capacity of the p-channel MOStransistor can be substantially equal to the parasitic capacity of then-channel MOS transistor. Accordingly, the switching characteristic canbe improved, and the noise generated by a current when the MOStransistors are turned ON or OFF can be reduced.

The present invention is not limited to the above-mentioned embodimentsbut can also be configured as follows.

The DC amplifier according to the present invention is not limited tothe circuit in the direct conversion system, but can be applied to othercircuits. The DC amplifier is not limited to the differentialamplification circuit according to the above-mentioned embodiments, butcan also be an amplification circuit of other configurations.

The crystal surface of silicon is not limited to a combination of thesurfaces (100) and (110), but can be a combination with another crystalsurface such as the surfaces (100) and (111).

According to the present invention, the DC offset and the 1/f noise ofthe DC amplifier can be reduced. Therefore, a circuit for compensatingfor a DC offset is not required. Furthermore, since the 1/f noise isreduced, the frequency characteristic of the DC amplifier can beimproved. Additionally, the influence of the channel length modulationeffect and the distortion of a signal in the DC amplifier can also bereduced.

1. A DC amplifier formed on a substrate of a semiconductor integratedcircuit, comprising a differential amplification circuit including a MISfield-effect transistor in which a projecting portion is formed by asilicon substrate having a first crystal surface as a primary surfaceand a second crystal surface as a side surface, terminated hydrogen onthe silicon surface is removed in plasma atmosphere of an inert gas,then a gate insulating film is formed on at least a part of a topsurface and the side surface of the projecting portion at a temperatureat or lower than about 550° C. in the plasma atmosphere, a gate isformed on the gate insulating film, and a drain and a source are formedon both sides enclosing the gate insulating film of the projectingportion.
 2. The DC amplifier according to claim 1, wherein a channel isformed on the first crystal surface of a top surface and the secondcrystal surface of the side surface of the projecting portion, and thechannel width of the MIS field-effect transistor is a total of a channelwidth of the top surface and a channel width of the side surface.
 3. TheDC amplifier according to claim 1, wherein the projecting portion hasthe top surface comprising a silicon surface (100), the side surfacecomprising a silicon surface (110), and the source and drain are formedon the projecting portion enclosing the gate and in left and right areasof the projecting portion of the silicon substrate.
 4. The DC amplifieraccording to claim 1, further comprising first and second MISfield-effect transistors for performing differential amplification on aninput signal, and a third MIS field-effect transistor which is connectedto a source or a drain of the first and second MIS field-effecttransistors and configures a constant current circuit.
 5. The DCamplifier according to claim 4, further comprising fourth and fifth MISfield-effect transistors which are connected between a source or a drainof the first and second MIS field-effect transistors and configure aconstant current circuit as a load of the first and second MISfield-effect transistors.
 6. A semiconductor integrated circuit,comprising on a same circuit substrate: a circuit including a p-channelMIS field-effect transistor and an n-channel MIS field-effect transistorin which a projecting portion is formed by a silicon substrate having afirst crystal surface as a primary surface and a second crystal surfaceas a side surface, terminated hydrogen on the silicon surface is removedin plasma atmosphere of an inert gas, then a gate insulating film isformed on at least a part of the top surface and the side surface of theprojecting portion at a temperature at or lower than about 550° C. inthe plasma atmosphere, a gate is formed on the gate insulating film, anda drain and a source are formed on both sides enclosing the gateinsulating film of the projecting portion; and a DC amplifier having adifferential amplification circuit including the p-channel MISfield-effect transistor or the n-channel MIS field-effect transistor. 7.The semiconductor integrated circuit according to claim 6, wherein gatewidths of a top surface and a side surface of the p-channel MISfield-effect transistor and the n-channel MIS field-effect transistorare set such that the current drive capability of the p-channel MISfield-effect transistor can be substantially equal to current drivecapability of the n-channel MIS field-effect transistor.
 8. Thesemiconductor integrated circuit according to claim 6, wherein thelimiter circuit comprises a CMOS circuit having the p-channel MISfield-effect transistor and the n-channel MIS field-effect transistor.